Signed saturating rounding doubling multiply-add high to accumulator (indexed)
Multiply then double all signed elements within each 128-bit segment of the first source vector and the specified signed element of the corresponding second source vector segment, and destructively add the rounded high half of each result to the corresponding elements of the addend and destination vector. Each destination element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1) )-1.
The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment, encoded in 1 to 3 bits depending on the size of the element.
It has encodings from 3 classes: 16-bit , 32-bit and 64-bit
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | i3h | 1 | i3l | Zm | 0 | 0 | 0 | 1 | 0 | 0 | Zn | Zda | |||||||||||
S |
if !HaveSVE2() && !HaveSME() then UNDEFINED; integer esize = 16; integer index = UInt(i3h:i3l); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(Zda);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | i2 | Zm | 0 | 0 | 0 | 1 | 0 | 0 | Zn | Zda | |||||||||||
size<1> | size<0> | S |
if !HaveSVE2() && !HaveSME() then UNDEFINED; integer esize = 32; integer index = UInt(i2); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(Zda);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | i1 | Zm | 0 | 0 | 0 | 1 | 0 | 0 | Zn | Zda | |||||||||||
size<1> | size<0> | S |
if !HaveSVE2() && !HaveSME() then UNDEFINED; integer esize = 64; integer index = UInt(i1); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(Zda);
<Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
<Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; integer eltspersegment = 128 DIV esize; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) operand3 = Z[da]; bits(VL) result; integer round_const = 1 << (esize - 1); for e = 0 to elements-1 integer segmentbase = e - (e MOD eltspersegment); integer s = segmentbase + index; integer element1 = SInt(Elem[operand1, e, esize]); integer element2 = SInt(Elem[operand2, s, esize]); integer element3 = SInt(Elem[operand3, e, esize]); integer res = (element3 << esize) + (2 * element1 * element2); Elem[result, e, esize] = SignedSat((res + round_const) >> esize, esize); Z[da] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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