Signed saturating rounding shift right unsigned narrow by immediate (bottom)
Shift each signed integer value in the source vector elements right by an immediate value, and place the rounded results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | tszh | 1 | tszl | imm3 | 0 | 0 | 0 | 0 | 1 | 0 | Zn | Zd | |||||||||||
U | R | T |
if !HaveSVE2() && !HaveSME() then UNDEFINED; bits(3) tsize = tszh:tszl; integer esize; case tsize of when '000' UNDEFINED; when '001' esize = 8; when '01x' esize = 16; when '1xx' esize = 32; integer n = UInt(Zn); integer d = UInt(Zd); integer shift = (2 * esize) - UInt(tsize:imm3);
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
|
<Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
<Tb> |
Is the size specifier,
encoded in
|
<const> |
Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsz:imm3". |
CheckSVEEnabled(); integer elements = VL DIV (2 * esize); bits(VL) operand = Z[n]; bits(VL) result; integer round_const = 1 << (shift-1); for e = 0 to elements-1 bits(2*esize) element = Elem[operand, e, 2*esize]; integer res = (SInt(element) + round_const) >> shift; Elem[result, 2*e + 0, esize] = UnsignedSat(res, esize); Elem[result, 2*e + 1, esize] = Zeros(); Z[d] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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