Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 0 | 0 | 1 | 1 | 0 | 1 | Rn | Rd | |||||||||||||
| U | immh | o1 | o0 | ||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); if immh<3> != '1' then UNDEFINED; integer esize = 8 << 3; integer datasize = esize; integer elements = 1; integer shift = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); boolean round = (o1 == '1'); boolean accumulate = (o0 == '1');
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 0 | 0 | 1 | 1 | 0 | 1 | Rn | Rd | |||||||||||||
| U | immh | o1 | o0 | ||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then UNDEFINED; integer esize = 8 << HighestSetBit(immh); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; integer shift = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); boolean round = (o1 == '1'); boolean accumulate = (o0 == '1');
| <V> |
Is a width specifier,
encoded in
|
| <d> |
Is the number of the SIMD&FP destination register, in the "Rd" field. |
| <n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
| <shift> |
For the scalar variant: is the right shift amount, in the range 1 to 64,
encoded in
| ||||||||||||
|
For the vector variant: is the right shift amount, in the range 1 to the element width in bits,
encoded in
|
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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