ST1W (scalar plus vector)

Scatter store of words from the active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements are not written to memory.

32-bit scaled offset

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 32; integer msize = 32; integer offs_size = 32; boolean offs_unsigned = xs == '0'; integer scale = 2;

32-bit unpacked scaled offset

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 32; boolean offs_unsigned = xs == '0'; integer scale = 2;

32-bit unpacked unscaled offset

32-bit unscaled offset

64-bit scaled offset

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 64; boolean offs_unsigned = TRUE; integer scale = 2;

64-bit unscaled offset

Assembler Symbols

<Zt>	Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Zm>	Is the name of the offset scalable vector register, encoded in the "Zm" field.

<mod>

Is the index extend and shift specifier, encoded in xs:

xs	<mod>
0	UXTW
1	SXTW

Operation

CheckNonStreamingSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(PL) mask = P[g]; bits(VL) offset; bits(VL) src; constant integer mbytes = msize DIV 8; if HaveMTEExt() then SetTagCheckedInstruction(TRUE); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n]; offset = Z[m]; src = Z[t]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned); bits(64) addr = base + (off << scale); Mem[addr, mbytes, AccType_NORMAL] = Elem[src, e, esize]<msize-1:0>;

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	1	0	1	1	Zm					1	xs	0	Pg			Rn					Zt
							msz<1>	msz<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	1	0	0	1	Zm					1	xs	0	Pg			Rn					Zt
							msz<1>	msz<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	1	0	0	0	Zm					1	xs	0	Pg			Rn					Zt
							msz<1>	msz<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	1	0	1	0	Zm					1	xs	0	Pg			Rn					Zt
							msz<1>	msz<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	1	0	0	1	Zm					1	0	1	Pg			Rn					Zt
							msz<1>	msz<0>