Contiguous store two-byte structures from two vectors (scalar index)
Contiguous store two-byte structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base and a 64-bit scalar index register and added to the base address. After each structure access the index value is incremented by two. The index register is not updated by the instruction.
Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive bytes in memory which make up each structure. Inactive structures are not written to memory.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Rm | 0 | 1 | 1 | Pg | Rn | Zt | ||||||||||||||
| msz<1> | msz<0> | ||||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 8; integer nreg = 2;
| <Zt1> |
Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. |
| <Zt2> |
Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xm> |
Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(PL) mask = P[g]; bits(64) offset; constant integer mbytes = esize DIV 8; array [0..1] of bits(VL) values; if HaveMTEExt() then SetTagCheckedInstruction(TRUE); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n]; offset = X[m]; for r = 0 to nreg-1 values[r] = Z[(t+r) MOD 32]; for e = 0 to elements-1 for r = 0 to nreg-1 if ElemP[mask, e, esize] == '1' then integer eoff = UInt(offset) + (e * nreg) + r; bits(64) addr = base + eoff * mbytes; Mem[addr, mbytes, AccType_NORMAL] = Elem[values[r], e, esize];
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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