Contiguous store four-doubleword structures from four vectors (immediate index)
Contiguous store four-doubleword structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base and an immediate index which is a multiple of 4 in the range -32 to 28 that is multiplied by the vector's in-memory size, irrespective of predication,
Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive doublewords in memory which make up each structure. Inactive structures are not written to memory.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | imm4 | 1 | 1 | 1 | Pg | Rn | Zt | |||||||||||||
| msz<1> | msz<0> | ||||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 64; integer offset = SInt(imm4); integer nreg = 4;
| <Zt1> |
Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. |
| <Zt2> |
Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. |
| <Zt3> |
Is the name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32. |
| <Zt4> |
Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(PL) mask = P[g]; constant integer mbytes = esize DIV 8; array [0..3] of bits(VL) values; if HaveMTEExt() then SetTagCheckedInstruction(n != 31); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n]; for r = 0 to nreg-1 values[r] = Z[(t+r) MOD 32]; for e = 0 to elements-1 for r = 0 to nreg-1 if ElemP[mask, e, esize] == '1' then integer eoff = (offset * elements * nreg) + (e * nreg) + r; bits(64) addr = base + eoff * mbytes; Mem[addr, mbytes, AccType_NORMAL] = Elem[values[r], e, esize];
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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