STNT1W (vector plus scalar)

Scatter store non-temporal words

Scatter store non-temporal of words from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory.

A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.

It has encodings from 2 classes: 32-bit unscaled offset and 64-bit unscaled offset

32-bit unscaled offset

313029282726252423222120191817161514131211109876543210
11100101010Rm001PgZnZt
msz<1>msz<0>

STNT1W { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]

if !HaveSVE2() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 32; integer msize = 32;

64-bit unscaled offset

313029282726252423222120191817161514131211109876543210
11100101000Rm001PgZnZt
msz<1>msz<0>

STNT1W { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]

if !HaveSVE2() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 64; integer msize = 32;

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the base scalable vector register, encoded in the "Zn" field.

<Xm>

Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

Operation

CheckNonStreamingSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) base; bits(64) offset; bits(VL) src; constant integer mbytes = msize DIV 8; if HaveMTEExt() then SetTagCheckedInstruction(TRUE); if AnyActiveElement(mask, esize) then base = Z[n]; offset = X[m]; src = Z[t]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then bits(64) addr = ZeroExtend(Elem[base, e, esize], 64) + offset; Mem[addr, mbytes, AccType_STREAM] = Elem[src, e, esize]<msize-1:0>;


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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