Store vector from ZA array
The ZA array vector is selected by the sum of the vector select register and an immediate, modulo the number of bytes in a Streaming SVE vector. The immediate is in the range 0 to 15. The memory address is generated by scalar base, plus the same optional immediate offset multiplied by the current vector length in bytes. This instruction is unpredicated.
The store is performed as a stream of byte elements in ascending element order, without any endian conversion.
This instruction does not require the PE to be in Streaming SVE mode, and it is expected that this instruction will not experience a significant slowdown due to contention with other PEs that are executing in Streaming SVE mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Rv | 0 | 0 | 0 | Rn | 0 | imm4 | ||||||||
if !HaveSME() then UNDEFINED; integer n = UInt(Rn); integer v = UInt('011':Rv); integer imm = UInt(imm4);
| <Wv> |
Is the 32-bit name of the vector select register W12-W15, encoded in the "Rv" field. |
| <imm> |
Is the vector select offset and optional memory offset, in the range 0 to 15, defaulting to 0, encoded in the "imm4" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
CheckSMEAndZAEnabled(); integer dim = SVL DIV 8; bits(32) idx = X[v]; integer vec = (UInt(idx) + imm) MOD dim; bits(SVL) src; bits(64) base; integer offset = imm * dim; if HaveTME() && TSTATE.depth > 0 then FailTransaction(TMFailure_ERR, FALSE); if n == 31 then if HaveMTEExt() then SetTagCheckedInstruction(FALSE); CheckSPAlignment(); base = SP[]; else if HaveMTEExt() then SetTagCheckedInstruction(TRUE); base = X[n]; src = ZAvector[vec]; boolean aligned = AArch64.CheckAlignment(base + offset, 16, AccType_NORMAL, TRUE); for e = 0 to dim-1 AArch64.MemSingle[base + offset, 1, AccType_NORMAL, aligned] = Elem[src, e, 8]; offset = offset + 1;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.