SUB (immediate)

Subtract an unsigned immediate from each element of the source vector, and destructively place the results in the corresponding elements of the source vector. This instruction is unpredicated.

The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280.

The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".

if !HaveSVE() && !HaveSME() then UNDEFINED; if size:sh == '001' then UNDEFINED; integer esize = 8 << UInt(size); integer dn = UInt(Zdn); integer imm = UInt(imm8); if sh == '1' then imm = imm << 8;

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

<imm>

Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.

<shift>

Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in sh:

sh	<shift>
0	LSL #0
1	LSL #8

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[dn]; bits(VL) result; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; Elem[result, e, esize] = element1 - imm; Z[dn] = result;

Operational information

If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

The MOVPRFX instruction must be unpredicated.
The MOVPRFX instruction must specify the same destination register as this instruction.
The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	1	size		1	0	0	0	0	1	1	1	sh	imm8								Zdn

SUB (immediate)

SUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}

Assembler Symbols

Operation

Operational information