SUNPKHI, SUNPKLO

Signed unpack and extend half of vector

Unpack elements from the lowest or highest half of the source vector and then sign-extend them to place in elements of twice their size within the destination vector. This instruction is unpredicated.

It has encodings from 2 classes: High half and Low half

High half

313029282726252423222120191817161514131211109876543210
00000101size110001001110ZnZd
UH

SUNPKHI <Zd>.<T>, <Zn>.<Tb>

if !HaveSVE() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer d = UInt(Zd); boolean unsigned = FALSE; boolean hi = TRUE;

Low half

313029282726252423222120191817161514131211109876543210
00000101size110000001110ZnZd
UH

SUNPKLO <Zd>.<T>, <Zn>.<Tb>

if !HaveSVE() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer d = UInt(Zd); boolean unsigned = FALSE; boolean hi = FALSE;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 RESERVED
01 H
10 S
11 D
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in size:

size <Tb>
00 RESERVED
01 B
10 H
11 S

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; integer hsize = esize DIV 2; bits(VL) operand = Z[n]; bits(VL) result; for e = 0 to elements-1 bits(hsize) element = if hi then Elem[operand, e + elements, hsize] else Elem[operand, e, hsize]; Elem[result, e, esize] = Extend(element, esize, unsigned); Z[d] = result;

Operational information

If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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