TLBI -- A64

TLBI <tlbi_op>{, <Xt>}
is equivalent to

SYS #<op1>, C8, <Cm>, #<op2>{, <Xt>}

and is the preferred disassembly when SysOp(op1,'1000',CRm,op2) == Sys_TLBI.

Assembler Symbols

<op1>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.

<Cm>	Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.

<op2>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

<tlbi_op>

Is a TLBI instruction name, as listed for the TLBI system instruction group, encoded in op1:CRm:op2:

op1	CRm	op2	<tlbi_op>	Architectural Feature
000	0001	000	VMALLE1OS	FEAT_TLBIOS
000	0001	001	VAE1OS	FEAT_TLBIOS
000	0001	010	ASIDE1OS	FEAT_TLBIOS
000	0001	011	VAAE1OS	FEAT_TLBIOS
000	0001	101	VALE1OS	FEAT_TLBIOS
000	0001	111	VAALE1OS	FEAT_TLBIOS
000	0010	001	RVAE1IS	FEAT_TLBIRANGE
000	0010	011	RVAAE1IS	FEAT_TLBIRANGE
000	0010	101	RVALE1IS	FEAT_TLBIRANGE
000	0010	111	RVAALE1IS	FEAT_TLBIRANGE
000	0011	000	VMALLE1IS	-
000	0011	001	VAE1IS	-
000	0011	010	ASIDE1IS	-
000	0011	011	VAAE1IS	-
000	0011	101	VALE1IS	-
000	0011	111	VAALE1IS	-
000	0101	001	RVAE1OS	FEAT_TLBIRANGE
000	0101	011	RVAAE1OS	FEAT_TLBIRANGE
000	0101	101	RVALE1OS	FEAT_TLBIRANGE
000	0101	111	RVAALE1OS	FEAT_TLBIRANGE
000	0110	001	RVAE1	FEAT_TLBIRANGE
000	0110	011	RVAAE1	FEAT_TLBIRANGE
000	0110	101	RVALE1	FEAT_TLBIRANGE
000	0110	111	RVAALE1	FEAT_TLBIRANGE
000	0111	000	VMALLE1	-
000	0111	001	VAE1	-
000	0111	010	ASIDE1	-
000	0111	011	VAAE1	-
000	0111	101	VALE1	-
000	0111	111	VAALE1	-
100	0000	001	IPAS2E1IS	-
100	0000	010	RIPAS2E1IS	FEAT_TLBIRANGE
100	0000	101	IPAS2LE1IS	-
100	0000	110	RIPAS2LE1IS	FEAT_TLBIRANGE
100	0001	000	ALLE2OS	FEAT_TLBIOS
100	0001	001	VAE2OS	FEAT_TLBIOS
100	0001	100	ALLE1OS	FEAT_TLBIOS
100	0001	101	VALE2OS	FEAT_TLBIOS
100	0001	110	VMALLS12E1OS	FEAT_TLBIOS
100	0010	001	RVAE2IS	FEAT_TLBIRANGE
100	0010	101	RVALE2IS	FEAT_TLBIRANGE
100	0011	000	ALLE2IS	-
100	0011	001	VAE2IS	-
100	0011	100	ALLE1IS	-
100	0011	101	VALE2IS	-
100	0011	110	VMALLS12E1IS	-
100	0100	000	IPAS2E1OS	FEAT_TLBIOS
100	0100	001	IPAS2E1	-
100	0100	010	RIPAS2E1	FEAT_TLBIRANGE
100	0100	011	RIPAS2E1OS	FEAT_TLBIRANGE
100	0100	100	IPAS2LE1OS	FEAT_TLBIOS
100	0100	101	IPAS2LE1	-
100	0100	110	RIPAS2LE1	FEAT_TLBIRANGE
100	0100	111	RIPAS2LE1OS	FEAT_TLBIRANGE
100	0101	001	RVAE2OS	FEAT_TLBIRANGE
100	0101	101	RVALE2OS	FEAT_TLBIRANGE
100	0110	001	RVAE2	FEAT_TLBIRANGE
100	0110	101	RVALE2	FEAT_TLBIRANGE
100	0111	000	ALLE2	-
100	0111	001	VAE2	-
100	0111	100	ALLE1	-
100	0111	101	VALE2	-
100	0111	110	VMALLS12E1	-
110	0001	000	ALLE3OS	FEAT_TLBIOS
110	0001	001	VAE3OS	FEAT_TLBIOS
110	0001	101	VALE3OS	FEAT_TLBIOS
110	0010	001	RVAE3IS	FEAT_TLBIRANGE
110	0010	101	RVALE3IS	FEAT_TLBIRANGE
110	0011	000	ALLE3IS	-
110	0011	001	VAE3IS	-
110	0011	101	VALE3IS	-
110	0101	001	RVAE3OS	FEAT_TLBIRANGE
110	0101	101	RVALE3OS	FEAT_TLBIRANGE
110	0110	001	RVAE3	FEAT_TLBIRANGE
110	0110	101	RVALE3	FEAT_TLBIRANGE
110	0111	000	ALLE3	-
110	0111	001	VAE3	-
110	0111	101	VALE3	-

<Xt>	Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.

Operation

The description of SYS gives the operational pseudocode for this instruction.

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	0	0	0	1	op1			1	0	0	0	CRm				op2			Rt
										L						CRn

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	0	0	0	1	op1			1	0	0	0	CRm				op2			Rt
										L						CRn

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	0	0	0	1	op1			1	0	0	0	CRm				op2			Rt
										L						CRn

TLBI

TLBI <tlbi_op>{, <Xt>} is equivalent to SYS #<op1>, C8, <Cm>, #<op2>{, <Xt>} and is the preferred disassembly when SysOp(op1,'1000',CRm,op2) == Sys_TLBI.

Assembler Symbols

Operation

TLBI <tlbi_op>{, <Xt>}
is equivalent to

SYS #<op1>, C8, <Cm>, #<op2>{, <Xt>}

and is the preferred disassembly when SysOp(op1,'1000',CRm,op2) == Sys_TLBI.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	0	0	0	1	op1			1	0	0	0	CRm				op2			Rt
										L						CRn