UADALP

Add pairs of adjacent unsigned integer values and accumulate the results into the overlapping double-width elements of the destination vector.

if !HaveSVE2() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer da = UInt(Zda);

Assembler Symbols

<Zda>

Is the name of the second source and destination scalable vector register, encoded in the "Zda" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	RESERVED
01	H
10	S
11	D

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>	Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in size:

size	<Tb>
00	RESERVED
01	B
10	H
11	S

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand_acc = Z[da]; bits(VL) operand_src = if AnyActiveElement(mask, esize) then Z[n] else Zeros(); bits(VL) result; for e = 0 to elements-1 if ElemP[mask, e, esize] == '0' then Elem[result, e, esize] = Elem[operand_acc, e, esize]; else integer element1 = UInt(Elem[operand_src, 2*e + 0, esize DIV 2]); integer element2 = UInt(Elem[operand_src, 2*e + 1, esize DIV 2]); bits(esize) sum = (element1 + element2)<esize-1:0>; Elem[result, e, esize] = Elem[operand_acc, e, esize] + sum; Z[da] = result;

Operational information

If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
- The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

The MOVPRFX instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.
The MOVPRFX instruction must specify the same destination register as this instruction.
The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	0	size		0	0	0	1	0	1	1	0	1	Pg			Zn					Zda
															U

UADALP

UADALP <Zda>.<T>, <Pg>/M, <Zn>.<Tb>

Assembler Symbols

Operation

Operational information