Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
This instruction is used by the alias MOV (to general).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 1 | 1 | 1 | 1 | Rn | Rd |
integer d = UInt(Rd); integer n = UInt(Rn); integer size; case Q:imm5 of when '0xxxx1' size = 0; // UMOV Wd, Vn.B when '0xxx10' size = 1; // UMOV Wd, Vn.H when '0xx100' size = 2; // UMOV Wd, Vn.S when '1x1000' size = 3; // UMOV Xd, Vn.D otherwise UNDEFINED; integer idxdsize = if imm5<4> == '1' then 128 else 64; integer index = UInt(imm5<4:size+1>); integer esize = 8 << size; integer datasize = if Q == '1' then 64 else 32;
<Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
<index> |
For the 32-bit variant: is the element index
encoded in
| ||||||||||
For the 64-bit variant: is the element index encoded in "imm5<4>". |
Alias | Is preferred when |
---|---|
MOV (to general) | imm5 == 'x1000' |
MOV (to general) | imm5 == 'xx100' |
if index == 0 then CheckFPEnabled64(); else CheckFPAdvSIMDEnabled64(); bits(idxdsize) operand = V[n]; X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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