Unsigned rounding shift left reversed vectors (predicated)
Shift active unsigned elements of the second source vector by corresponding elements of the first source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Inactive elements in the destination vector register remain unmodified.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | size | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | Pg | Zm | Zdn | |||||||||||
| Q | R | N | U | ||||||||||||||||||||||||||||
if !HaveSVE2() && !HaveSME() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer m = UInt(Zm); integer dn = UInt(Zdn);
| <Zdn> |
Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[m] else Zeros(); bits(VL) operand2 = Z[dn]; bits(VL) result; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer element = UInt(Elem[operand1, e, esize]); integer shift = ShiftSat(SInt(Elem[operand2, e, esize]), esize); integer round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift integer res = (element + round_const) << shift; Elem[result, e, esize] = res<esize-1:0>; else Elem[result, e, esize] = Elem[operand2, e, esize]; Z[dn] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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