Unsigned shift right and accumulate (immediate)
Shift right by immediate each unsigned element of the source vector, inserting zeroes, and add the truncated intermediate result destructively to the corresponding elements of the addend vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | tszh | 0 | tszl | imm3 | 1 | 1 | 1 | 0 | 0 | 1 | Zn | Zda | ||||||||||||
| R | U | ||||||||||||||||||||||||||||||
if !HaveSVE2() && !HaveSME() then UNDEFINED; bits(4) tsize = tszh:tszl; integer esize; case tsize of when '0000' UNDEFINED; when '0001' esize = 8; when '001x' esize = 16; when '01xx' esize = 32; when '1xxx' esize = 64; integer n = UInt(Zn); integer da = UInt(Zda); integer shift = (2 * esize) - UInt(tsize:imm3);
| <Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <const> |
Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsz:imm3". |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[da]; bits(VL) result; for e = 0 to elements-1 integer element = UInt(Elem[operand1, e, esize]) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; Z[da] = result;
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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