Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.
The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | Rn | Rd |
integer d = UInt(Rd); integer n = UInt(Rn); if size == '11' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize;
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Tb> |
Is an arrangement specifier,
encoded in
|
<Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
<Ta> |
Is an arrangement specifier,
encoded in
|
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand = V[n]; bits(datasize) result; bits(2*esize) element; for e = 0 to elements-1 element = Elem[operand, e, 2*esize]; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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