Add (immediate), setting flags, adds a register value and an optionally-shifted immediate value, and writes the result to the destination register. It updates the condition flags based on the result.
This instruction is used by the alias CMN (immediate).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | sh | imm12 | Rn | Rd | |||||||||||||||||||
| op | S | ||||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); integer datasize = if sf == '1' then 64 else 32; boolean sub_op = (op == '1'); boolean setflags = (S == '1'); bits(datasize) imm; case sh of when '0' imm = ZeroExtend(imm12, datasize); when '1' imm = ZeroExtend(imm12 : Zeros(12), datasize);
| <Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Wn|WSP> |
Is the 32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field. |
| <Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Xn|SP> |
Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field. |
| <shift> |
Is the optional left shift to apply to the immediate, defaulting to LSL #0 and
encoded in
|
| Alias | Is preferred when |
|---|---|
| CMN (immediate) | Rd == '11111' |
bits(datasize) result; bits(datasize) operand1 = if n == 31 then SP[] else X[n]; bits(datasize) operand2 = imm; bits(4) nzcv; bit carry_in; if sub_op then operand2 = NOT(operand2); carry_in = '1'; else carry_in = '0'; (result, nzcv) = AddWithCarry(operand1, operand2, carry_in); if setflags then PSTATE.<N,Z,C,V> = nzcv; if d == 31 && !setflags then SP[] = result; else X[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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