Compare Negative (immediate) adds a register value and an optionally-shifted immediate value. It updates the condition flags based on the result, and discards the result.
This is an alias of ADDS (immediate). This means:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | sh | imm12 | Rn | 1 | 1 | 1 | 1 | 1 | |||||||||||||||
op | S | Rd |
CMN <Wn|WSP>, #<imm>{, <shift>}
is equivalent to
ADDS WZR, <Wn|WSP>, #<imm> {, <shift>}
and is always the preferred disassembly.
CMN <Xn|SP>, #<imm>{, <shift>}
is equivalent to
ADDS XZR, <Xn|SP>, #<imm> {, <shift>}
and is always the preferred disassembly.
<Wn|WSP> |
Is the 32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field. |
<Xn|SP> |
Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field. |
<imm> |
Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field. |
<shift> |
Is the optional left shift to apply to the immediate, defaulting to LSL #0 and
encoded in
|
The description of ADDS (immediate) gives the operational pseudocode for this instruction.
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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