Broadcast indexed element to vector (unpredicated)
Unconditionally broadcast the indexed source vector element into each element of the destination vector. This instruction is unpredicated.
The immediate element index is in the range of 0 to 63 (bytes), 31 (halfwords), 15 (words), 7 (doublewords) or 3 (quadwords). Selecting an element beyond the accessible vector length causes the destination vector to be set to zero.
This instruction is used by the alias MOV (SIMD&FP scalar, unpredicated).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | imm2 | 1 | tsz | 0 | 0 | 1 | 0 | 0 | 0 | Zn | Zd | |||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; bits(7) imm = imm2:tsz; integer esize; integer index; case tsz of when '00000' UNDEFINED; when '10000' esize = 128; index = UInt(imm<6:5>); when 'x1000' esize = 64; index = UInt(imm<6:4>); when 'xx100' esize = 32; index = UInt(imm<6:3>); when 'xxx10' esize = 16; index = UInt(imm<6:2>); when 'xxxx1' esize = 8; index = UInt(imm<6:1>); integer n = UInt(Zn); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
| <imm> |
Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz". |
| Alias | Is preferred when |
|---|---|
| MOV (SIMD&FP scalar, unpredicated) | BitCount(imm2:tsz) == 1 |
| MOV (SIMD&FP scalar, unpredicated) | BitCount(imm2:tsz) > 1 |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) result; bits(esize) element; if index >= elements then element = Zeros(); else element = Elem[operand1, index, esize]; result = Replicate(element); Z[d] = result;
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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