Move indexed element or SIMD&FP scalar to vector (unpredicated)
Unconditionally broadcast the SIMD&FP scalar into each element of the destination vector. This instruction is unpredicated.
This is an alias of DUP (indexed). This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | imm2 | 1 | tsz | 0 | 0 | 1 | 0 | 0 | 0 | Zn | Zd | |||||||||||||
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
| <imm> |
Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz". |
| <V> |
Is a width specifier,
encoded in
|
| <n> |
Is the number [0-31] of the source SIMD&FP register, encoded in the "Zn" field. |
The description of DUP (indexed) gives the operational pseudocode for this instruction.
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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